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CXA3117AN
IF Amplifier for M-ary FSK Pagers
Description The CXA3117AN is a low current consumption FM IF amplifier which employs the newest bipolar process. It is suitable for M-ary FSK pagers. Features * Low current consumption: 1.1mA (typ. at VCC = 1.4V) * Low voltage operation: VCC = 1.1 to 4.0V * Small package 24-pin SSOP * Second mixer and oscillator * Needless of IF decoupling capacitor * Reference power supply for operational amplifier and comparator * Bit rate filter with variable cut-off * Misoperation prevention function for continuous data * RSSI function * IF input, VCC standard * Quick charge by the detector output sense method Applications * M-ary FSK pagers * Double conversion pagers Block Diagram and Pin Configuration
REG OUT REG CONT CHG OFF
24 pin SSOP (Plastic)
Structure Bipolar silicon monolithic IC Absolute Maximum Ratings * Supply voltage * Operating temperature * Storage temperature * Allowable power dissipation Operating Condition Supply voltage
7.0 V VCC Topr -20 to +75 C Tstg -65 to +150 C PD 417 mW
VCC
1.1 to 4.0
V
NRZ OUT
LVA OUT
CHARGE
MIX IN
AUDIO
L.C. OUT
GND
B.S.
24
23
22
21
20
19
18
17
16
15
14
13 RSSI
GND MIX OSC REG
LVA CHARGE
LEVEL COMP
QUAD_DET IF_LIM FILTER
1
2
3
4
5
6
7
8
9
10
11
12
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
OSC OUT
TH CONT
-1-
FSK REF
MIX OUT
OSC IN
FIL SW
E97220A8Z
QUAD
IF IN
VCC
C1
C2
C3
RSSI
CXA3117AN
Pin Description Pin No. Symbol Pin voltage Equivalent circuit
VCC
Description
1
OSC IN
1.4V
1
15k 72 2
300 15k
Connects the external parts of crystal oscillator circuit. A capacitor and crystal oscillator are connected to these pins and VCC.
2
OSC OUT
0.7V
GND VCC 1.5k 3
3
MIX OUT
1.3V
Mixer output. Connect a 455kHz ceramic filter between this pin and IF IN.
GND
4
VCC
VCC 1.5k 20k 20k 1.5k
Power supply.
5
IF IN
1.4V
5
IF limiter amplifier input.
GND VCC
6
TH CONT
--
6
25k GND VCC
Determines the level comparator threshold value. Threshold value can be adjusted by inserting the resistor between Pin 6 and VCC. Normally, short to VCC.
7
FSK REF
0.2V
72 7
Connects the capacitor that determines the low cut-off frequency for the entire system.
GND
-2-
CXA3117AN
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC 20k 22k
Description
8
QUAD
1.4V
8 20p
Connects the phase shifter of FM detector circuit.
GND
VCC
9 10 11
C1 C2 C3
0.2V
9 10 11 35k 50k GND
Connects the capacitor that determines the LPF cut-off.
12 72 20k
12
FIL SW
--
140k GND
Switches the LPF cut-off. Cut-off is decreased by setting this pin high. (Applied voltage range: -0.5V to +7.0V)
VCC 7k 7k
13
RSSI
0.1V
13 70k GND
RSSI circuit output.
14 72 20k
14
CHG OFF
--
100k GND
Sets off the quick charge circuit current. The charge current is off by setting Pin 18 low and Pin 14 high.
-3-
CXA3117AN
Pin No.
Symbol
Pin voltage
15
Equivalent circuit
Description
15 19 20
L.C. OUT NRZ OUT LVA OUT
-- -- --
19 20
72
Level comparator, NRZ comparator and LVA comparator outputs. They are open collectors. (Applied voltage range: -0.5V to +7.0V)
GND
VCC
72
16
AUDIO
0.2V
16 72
Level comparator and NRZ comparator inputs. The filter circuit output is connected.
GND
17 72 20k
17
B.S.
--
140k GND
Controls the battery saving. Setting this pin low suspends the operation of IC. (Applied voltage range: -0.5V to +7.0V)
20k 18
18
CHARGE
--
100k GND
Controls the speed of the quick charge circuit. Set this pin high to execute the quick charge. (Applied voltage range: -0.5V to +7.0V)
VCC
21
REG CONT
--
72 21
Output for internal constant-voltage source amplifier. Connect the base of PNP transistor. (Current capacity: 100A)
GND VCC
22
REG OUT
1.0V
78k 22
1k
Constant-voltage source output. Controlled to maintain 1.0V.
22k GND
23
GND
-- -4-
Ground
CXA3117AN
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC 2k 4.16k 4.16k
Description
24
MIX IN
1.4V
24
Mixer input.
GND
Electrical Characteristics (VCC = 1.4V, Ta = 25C, Fs = 21.7MHz, FMOD = 1.6kHz, FDEV = 4.8kHz, AMMOD = 30%) Item Current consumption Current consumption AM rejection ratio Symbol ICC ICCS AMRR Conditions Measurement circuit 1, V2 = 1.0V Measurement circuit 1, V2 = 0V Measurement circuit 2, 30k LPF Measurement circuit 4, Vin = 0.3V Measurement circuit 3, Vin = 0.1V Measurement circuit 3, Vin = 0.1 to 0.3V Measurement circuit 5 Measurement circuit 5 Output current 0A Measurement circuit 6, V1 = 1.4 to 1.0V Measurement circuit 6, V1 = 1.0V Measurement circuit 7 Measurement circuit 2 -- -- Measurement circuit 2, Data filter fc = 2.4kHz When Pin 6 is shorted to Vcc Min. 0.7 -- 25 -- -- 0 100 -- 0.95 1.05 -- -- 50 0.9 -- -- Typ. 1.1 6 -- -- -- 10 -- -- 1.00 1.10 -- -- 63 -- -- -108 Max. 1.35 10 -- 0.4 5.0 20 -- 0.4 1.05 1.15 5.0 0.4 80 -- 0.35 -- Unit mA A dB V A mV A V V V A V mVrms V V dBm
NRZ output saturation voltage VSATNRZ NRZ output leak current NRZ hysteresis width VB output current VB output saturation voltage REG OUT voltage LVA operating voltage LVA output leak current LVA output saturation voltage Detector output voltage Logic input voltage high level Logic input voltage low level Limiting sensitivity Detector output level ratio deviation to level comparator window width Level comparator output saturation voltage Level comparator output leak current RSSI output offset Mixer input resistance Mixer output resistance IF limiter input resistance ILNRZ VTWNRZ IOUT VSATVB VREG VLVA ILLVA VSATLVA VODET VTHBSV VTLBSV VIN (LIM)
VLCWR
-15
0
+15
%
VSATLC ILLC VORSSI RINLIM ROUTMIX RINLIM
Measurement circuit 9 Measurement circuit 8 Measurement circuit 10 -- -- -- -5-
-- -- -- 1.6 1.2 1.2
-- -- 150 2.0 1.5 1.5
0.4 5.0 300 2.4 1.8 1.8
V A mV k k k
CXA3117AN
Electrical Characteristics Measurement Circuit
Vin 10p to 120p 1.8 V2 24 23 22 21 20 19 18 17 16 15 14 13 1000p 24 23 22 21 20 19 18 17 16 15 14 13 V2 1V
1
2
3 VCC
4
5
6
7
8
9
10
11
12
1 2 22p
3
4
5
6
7
8
9
10
11 12
V1 1.4V
15p VCC
1 V1 1.4V
1200p 1200p
8.2k
1200p
Measurement circuit 1
Measurement circuit 2
100k 24 23 22 21 20 19 18 17
V2 1V
50A
V2 1V 18 17 16 15 14 13
16 15
14
13
24 23
22
21 20 19
1
2
3 VCC
4
5
6
7
8
9
10
11
12 Vin
1
2
3 VCC
4
5
6
7
8
9
10
11
12 Vin
V1 1.4V
V1 1.4V
Measurement circuit 3
Measurement circuit 4
-6-
CXA3117AN
100A GND V3 0.5V V2 1V 22 21 20 19 18 17 16 15 14 13 24 23 22 V2 1V 20 19 18 17 16 15 14 13
100k 21
24 23
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3 VCC
4
5
6
7
8
9
10
11
12
VCC
V1 1.4V
V1 1.4 to 1.0V
GND
Measurement circuit 5
Measurement circuit 6
50A
V2 1V 19 18 17 16 15 14 13 24 23 22 21 20 19
V2 1V 18 17
100k 16 15 14 13
24 23
22
21 20
1
2
3
4
5
6
7
8
9
10
11 12
1
2
3 VCC
4
5
6
7
8
9
10
11 12 Vin 0.2V
VCC
V1 1.4V
V1 1.4V
Measurement circuit 7
Measurement circuit 8
V2 1V 24 23 22 21 20 19 18 17
50A V2 1V 16 15 14 13 24 23 22 21 20 19 18 17 16 15 14 13
100P
1
2
3 VCC
4
5
6
7
8
9
10
11 12 Vin 0.1V
1
2
3 VCC
4
5
6
7
8
9
10
11 12
V1 1.4V
V1 1.4V
Measurement circuit 9 -7-
Measurement circuit 10
Application circuit
REG
LVA
NRZ
LEVEL
RSSI
GND R4 220 C9 0.01 PNP GND GND R5 100k R6 100k S4 R8 100k S3 18 17 16
AUDIO L.C. OUT CHG_ OFF
GND
C1 10p to 120p GND C14 100p 14 13 GND GND
RF S2
SMA L1 1.8H GND 23 22 20
VB_ REG
C6 10 C3 GND 1000p 21 LVA
NRZ_ CHARGE BS COMP
GND 19 15
24
GND REG CHARGE QUAD_DET IF_LIM FILTER
LEVEL COMP
RSSI
MIX
OSC
FIL_SW
1 2 3 R7 6.8k C10 1 CERAFIL GND C7 10 GND C8 0.01 DISC C5 15p 7 4 8
C4 22p
5
6
9 C11 1100p
(100p + 1000p)
10 C12 680p GND
11 C13 1420p
12 S1
(1200p + 220p)
XTAL
GND
GND
VCC
CXA3117AN
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
AUDIO
-8-
CXA3117AN
Application Note 1) Power Supply The CXA3117AN, with the built-in regulator, is designed to permit stable operation at the wide range of supply voltage from 1.1 to 4.0V. Decouple the wiring to VCC (Pin 4) as close to the pin as possible. 2) Oscillator Input Oscillator input method a) Using Pins 1 and 2, input self-excited oscillation signal through the composition of a Colpitts type crystal oscillator circuit. Connect the capacitors attached to the crystal and Pin 2 to VCC. b) Directly input a local oscillation signal to Pin 1.
1
2
3 Ceramic filter
1
2
3 Ceramic filter
VCC From local signal
Fig. 1 3) Mixer The mixer is of double-balance type. Pin 24 is the input pin. Input though a suitable matching circuit. The input impedance is 2.0k. Pin 3 serves as the output pin for the mixer, and a load resistance of 1.5k is incorporated. 4) IF Filter The filter to be connected between this mixer output and the IF limiter amplifier input should have the following specifications. Connect the ground pin of the IF filter to VCC. I/O impedance : 1.5k 10% Bandwidth : Changes according to applications. 5) IF Limiter Amplifier The gain of this IF limiter amplifier is approximately 100dB. Take notice of the following points in making connection to the IF limiter amplifier input pin (Pin 5). a) Wiring to the IF limiter amplifier input (Pin 5) should be as short as possible. b) As the IF limiter amplifier output appears at QUAD (Pin 8), wiring to the ceramic discriminator connected to QUAD should be as short as possible to reduce the interference with the mixer output and IF limiter amplifier input.
3 4 5 6 7 8 9
VCC
Wire as short and apart as possible
As short as possible
Fig. 2 -9-
CXA3117AN
6) Quick Charge In order to hasten the rising time from when power is turned on, the CXA3117AN features a quick charge circuit. Therefore, the quick charge circuit eliminates the need to insert a capacitor between the detector output and the LPF as is the case with conventional ICs, but a capacitor should be connected to Pin 7 to determine the average signal level during steady-state reception. The capacitance value connected to Pin 7 should be chosen such that the voltage does not vary much due to discharge during battery saving. Connect a signal for controlling the quick charge circuit to Pin 18. Setting this pin high enables the quick charge mode, and setting this pin low enables the steady-state reception mode. Quick charge is used when the power supply is turned on. The battery saving must be set high at the time. Connect Pin 18 to GND when quick charge is not being used.
Power supply to the IC (Pin 4)
Quick charge (Pin 18)
5ms
1ms
1ms
Battery saving control (Pin 17)
A T2 T1 T3 T4
A
A
Fig. 3 Example when the Pin 7 REF capacitance value is 1F T1 in Fig. 3: 2-level data setting time after quick charge When the input frequency offset is within 4.8kHz: 0ms T2 in Fig. 3: 4-level data setting time after quick charge When the input frequency offset is within 1.6kHz or less: 0ms When the input frequency offset is within 3kHz or less: 500ms or less T3 in Fig. 3: 4-level data is obtained T4 in Fig. 3: 2-level data is obtained
- 10 -
CXA3117AN
7) Detector The detector is of quadrature type. To perform phase shift, connect a ceramic discriminator to Pin 8. The phase shifting capacitor for the quadrature detector is incorporated. The FM (FSK) signal demodulated with the detector is output to AUDIO (Pin 16) through the internal primary LPF. The AUDIO output is the anti-phase output to the NRZ OUT. The CDBM455C50 (MURATA MFG. CO., LTD.) ceramic discriminator is recommended for the CXA3117AN. For the 2-level system, the CDBM455C28 can also be used.
7
8
9
6.8k Ceramic discriminator CDBM455C50 VCC
Fig. 4 The detector output level is changed according to the resistance value connected to Pin 8. 8) Filter Buffer, Level Comparator and NRZ Comparator The LPF circuit is built in this IC. The LPF output is connected internally to the NRZ comparator, level comparator and quick charge circuit.
19
16
15 L. C. LPF 0.2V DET
7
Fig. 5 Using the LPF, remove noise from the demodulated signal and input the signal to the above three circuits.
- 11 -
CXA3117AN
8)-1. LPF Constant The data filter cut-off (fc) is expressed with the following equation. fc1 = fc2 = 1 2C11R 1 2 1 ,Q= C12 C13 R2 C12 C13
C11 to C13: External capacitance (Pin 9 to Pin 11) R: IC internal resistance R is approximately 55k 20% when Pin 12 is low. The table below shows the example of constants to data rate. Capacitance (pF) H L Pin 12 filter switch H L H L H L 1500 Pin 9 Pin 10 Pin 11 Pin 9 Pin 10 Pin 11 1100 680 1420 1100 680 1420 6800 fc (Hz) -- 430 950 1900 1000 2000 1000 2000 Data rate -- 512bps (2 levels) 1200bps (2 levels) 2400bps (2 levels) 1600bps (2 levels) 3200bps (2 levels) 3200bps (4 levels) 6400bps (4 levels)
8)-2. Comparator Output The level comparator and the NRZ comparator shape the waveform of this input signal and output it as a square wave. The comparator output stage is for open collector. Thus, if the CPU is of CMOS type and the supply voltage is different, a direct interface as illustrated in the figure below can be implemented.
VCC 1.4V VCC 4 CMOS power supply
(15) 19 Comparator output CMOS IC
Fig. 6
- 12 -
CXA3117AN
8)-3. Level Comparator Output The level comparator characteristics are as shown in the figure below. Therefore, a high signal is output at the bit border even if the input signal is a 4.8kHz signal. This high output interval varies according to the frequency response of the bit rate filter, and widens as the cut-off frequency becomes lower. The decoder avoids this high interval when processing data.
Input signal
H
Output
L -4.8 -1.6 f0 +1.6 +4.8 Level comparator output
Input frequency deviation [kHz]
9) REG CONT Controls the base bias of the external transistors. 10) LVA OUT This pin goes high (open) when the supply voltage becomes low. Since the output is an open collector, it can be used to directly drive CMOS device. The setting voltage of the LVA is 1.10V (typ.), and it possesses a hysteresis with respect to the supply voltage. The hysteresis width is 10mV (typ.). 11) B.S. Operation of the CXA3117AN can be halted by setting this pin low. This pin can be connected directly to CMOS device. The current consumption during battery saving is 10A or less (at 1.4V).
B.S. 17
Fig. 7
- 13 -
CXA3117AN
12) M-ary (M = 2- or 4-level) FSK Demodulation System 12)-1. Output Waveform Polarity discrimination output and MSB comparator output are used to demodulate the 4-level waveform shown below. [4-level FSK demodulating waveform]
+4.8kHz
+1.6kHz 01 -1.6kHz 00 10 11 01 10 00
-4.8kHz
[NRZ OUT] Polarity discrimination output
POS
(When the input frequency is higher than the local frequency)
0
0
1
1
0
1
0
NEG
(The polarity can be inverted by setting the local frequency higer than the input frequency.)
[L.C. OUT] MSB comparator output
1.6kHz
1
0
0
1
1
0
0
4.8kHz
The 4-level FSK demodulating data is divided into an NRZ OUT and L.C. OUT shown above. Here, the NRZ OUT corresponds to a conventional NRZ comparator output. The L.C. OUT is made comparing the demodulated waveform amplitude to the IC internal reference voltage levels. When the threshold value of L.C. OUT is not appropriate to the detector output, the resistance value on Pin 8 should be varied for the detector output level adjustment or the resistor should be inserted between Pin 6 and VCC for the level comparator threshold value adjustment. For the 2-level FSK demodulation, it corresponds to a conventional NRZ comparator output.
6 R VCC
- 14 -
CXA3117AN
12)-2. 4-level Signal and Threshold Value For Sony pager ICs, the demodulated signal is optimally matched to the NRZ comparator threshold value by the curve correction operation described in 13) as shown in the figure below. (operation point correction using a feedback loop filter)
Level comparator 1 Offset correction circuit Detector output NRZ comparator
Level comparator 2
Operation point correction (The comparator threshold value is fixed.) The level comparator threshold value can be adjusted by varying the detector output level, which is achieved by varying the discriminator dumping resistance. (AC gain adjustment)
Level comparator threshold value 1 NRZ threshold value = Demodulated signal average voltage Level comparator threshold value 2
AC gain adjustment
- 15 -
CXA3117AN
12)-3. Offset Amount and Threshold Value Immediately after power-on when the REF capacitor is not charged with the correction voltage, if the input frequency has an offset, some time is required to correct this offset. In addition, the times required to obtain 2-level and 4-level data differ according to the offset amount. a) 2-level signals In the case of 2-level signals, correct data is obtained when the offset amount is smaller than the detector output amplitude. This is 75mV or less when the detector output level is 150mVp-p which corresponds to within 4.8kHz when converted to a frequency by the S curve. Thus, 2-level data is obtained without an operation point correction time lag when the frequency offset is within 4.8kHz.
NRZ threshold value offset
b) 4-level signals In the case of 4-level signals, correct data is obtained when the offset amount is less than 1/3 of the detector output amplitude (during 4.8kHz DEV). This is 25mV or less when the detector output level is 150mVp-p which corresponds to 1.6kHz or less when converted to a frequency by the S curve, . Thus, 4level data is obtained without an operation point correction time lag when the frequency offset is within 1.6kHz.
Level comparator threshold value 1 NRZ threshold value offset Level comparator threshold value 2
As shown above, 4-level signals have an allowable offset range 1/3 that of 2-level signals. When the offset exceeds this allowable range, time is required to determine the operation point and obtain correct data through feedback. Also, even if the offset is within the allowable range, the output pulse duty changes until the offset is 0.
- 16 -
CXA3117AN
13) Principle of Quick Charge Operation BUF in Fig. 8 is the detector buffer amplifier and COMP is the level comparator or the NRZ comparator. The CXA3117AN has a feedback loop from the comparator input to the input circuit of the detector output buffer. This equalizes the average value of the comparator input voltage to the reference voltage, with the quick charge circuit of CHG being set in the feedback loop. Switching the current of the quick charge circuit enables reduction of the rise time. In this block, CHG is a comparator which compares input voltages and outputs a current based on this comparison. The current on CHG is switched between high and low at Pin 18. When the power is turned on, switch the current to high to increase the charge current at C in Fig. 8 and shorten the time constant. During steady-state reception mode, switch the current to low, lengthening the charge time constant and allowing for stable data retrieval. Also, controlling Pin 14 can make the current off. This is effective when the same data are received continuously.
AUDIO BUF LPF 16 COMP 19 CHG
FSK REF
7 C
Reference voltage
Fig. 8 13)-1. Slow Charge Mode , Quick Charge Mode During slow charge mode and Quick Charge Mode, if the RF system frequency is deviated, etc., and the demodulated output has an offset voltage, feedback is applied to correct this offset voltage. Here, feedback is applied so that the average value of the audio output voltage matches the internal regulator voltage. This feedback shifts the S curve up and down in a parallel manner.
Offset Reference voltage
S curve S curve Reference voltage
When the RF system frequency is deviated, there is no correction so an offset occurs.
Input signal
During slow charge mode, the S curve shifts to correct the offset.
- 17 -
Input signal
f0
f0
CXA3117AN
14) S Curve Characteristics Even if the IF IN input signal frequency is deviated, the feedback is applied to the AUDIO operating point so as to match it to the comparator reference voltage by the quick charge operation shown in Fig. 8. Therefore, this feedback must be halted in order to evaluate the S curve characteristics. To execute the evaluation, measure the average voltage on Pin 16 first and input this voltage to Pin 7 from the external power supply. 15) Control Pins The function controls are as shown below. Pin No. Symbal Function Input high Input low 12 FIL SW Data filter cut-off control fc: Low fc: High 14 CHG OFF 17 B.S. 18 CHARGE
Pin 7 charge current Battery saving mode Pin 7 charge speed control control control Quick charge Slow charge off IC operation Slow charge Slow charge operation Sleep
Note) Pin 14 control should be performed with Pin 18 low. When each function is not controlled externally, set it to the state with an asterisk ().
16) Misoperation Prevention Function for Continuous Data The offset to the comparator threshold value of the detector output is canceled with the feedback loop indicated in the paragraph 13). This operation assumes that "0" and "1" are in equal numbers in the data. The offset is occurred when the "0" or "1" data are received continuously. In this case, setting Pin 14 high to make the charge current off prevents the offset occurrence. Without using this function, the stability for the same data continuously received depends on the capacitance value on Pin 7 shown in the paragraph 13). When this capacitance value is increased, the data is demodulated more stably; however, it takes more time for the IC to rise. If this function is not used, be sure to connect Pin 14 to GND.
Reception signal
Sync part
Data
Sync part
Data
CHG OFF H (Pin 14) L
Fig. 9
- 18 -
CXA3117AN
17) REF Capacitance Value and Charge Time, Hold Time The REF capacitance is the feedback loop time constant of the S curve. This determines the detector output low frequency cut-off, IC rise characteristics and operating voltage hold characteristics during battery saving. When the REF capacitance is reduced: 1. The detector output low frequency cut-off becomes higher. 2. The IC rise characteristics become faster. 3. The operating voltage hold characteristics during battery saving become shorter. Of these, 1 has little effect on FSK, so a capacitance value that matches the used system should be selected in consideration of 2 and 3. 17)-1. Example of IC Rise Characteristics Immediately After Power-on
[s] 1.0 When the REF capacitance is 1F
0.5
0 -3 f0 +3 [kHz]
Offset frequency and T2 (after power-on until 4-level data is obtained)
17)-2. Example of Operating Voltage Hold Characteristics When the REF capacitance is 1F, the S curve hold voltage variation is a value that has no effect on the rise of the 4-level data after 5 minutes of battery saving as shown below. Offset voltage after 5 minutes of battery saving: 10mV or less
- 19 -
CXA3117AN
18) Sensitivity Adjustment Method The constants shown in the Application Circuit diagram are for the standard external parts. However, adjustment may be necessary depending on the conditions of use, characteristics of external parts, and the RF system circuit and decoder connected to the IF IC, etc. Adjust the sensitivity according to the following procedures. a) MIX IN matching When using a matching circuit between the RF system circuit and MIX IN of the CXA3117N, adjust the trimmer to obtain the optimal sensitivity while monitoring the AUDIO output. b) Local input level The mixer circuit gain is dependent on the local signal input level to OSC IN. The input level to OSC IN should be set as high as possible within the range of -6 to +2dBm as shown in the graph of "Local input level vs. Mixer gain characteristics". However, care should be taken as raising the input level above +2dBm will cause the sensitivity to drop. When creating the local signal using the internal oscillator circuit, the oscillation level varies according to the external capacitances attached to Pins 1 and 2 and the characteristics of the used crystal. Therefore, be sure to adjust the external capacitance values attached to Pins 1 and 2 according to the crystal characteristics.
OSC
1
2
C1 VCC
C2
C1 and C2 have the following range in the figure above. C1 C2 C1 = C2 to C1 = 5C2 As for the ratio of C1 to C2, the oscillation stabilizes as C1 approaches equality with C2. The oscillation level decreases as the C1 and C2 values become larger, and increases as the C1 and C2 values become smaller. Use a FET probe to confirm the local input level. c) LPF constant The data filter cut-off may need to be changed depending on the characteristics of the connected decoder. Adjust the capacitance values of Pins 9 to 12 while checking the incoming sensitivity including the decoder. If the capacitance values are too large, the detector output waveform will deviate at high data rates, causing the sensitivity to drop. Conversely, if the capacitance values are too small, the LPF will be easily affected by noise, causing the sensitivity to drop. Adjust capacitance values of Pins 9 to 12 so that the capacitance value described in "16) LPF Constant" becomes smaller.
- 20 -
CXA3117AN
d) Detector output level The NRZ comparator and level comparator threshold values are fixed for the CXA3117AN. In the case of 4level signals, the relationship between the level comparator threshold value and the detector output level affects the sensitivity. The detector output level can be adjusted by the resistance attached to Pin 8. Increasing the resistance value also increases the output level, and vice versa. The Pin 8 resistance value differs according to the ceramic discriminator attached to Pin 8. When the discriminator is changed to a different type, the resistance value must be adjusted. Adjust the resistance value while monitoring the level comparator output waveform or the sensitivity including the decoder. e) Quick charge circuit The CXA3117AN has a feedback circuit that corrects the detector output operation point in order to correct the IF frequency deviation. When the IF frequency deviation amount is large, correction takes time and may lower the sensitivity. Adjust the oscillator frequency of the local oscillator so that the center frequency of the signal input to Pin 5 (IF IN) is as close to 455kHz as possible. 19) CXA3117AN Standard Board Description * Outline This board contains the external parts shown in the Application Circuit in order to evaluate CXA3117AN operation. * Features The following CXA3117AN basic operations can be checked. 1) Varying the data filter cut-off 2) Battery saving and other mode switching 3) NRZ output and level comparator output pins * Method of use 1) Input the CXA3117AN supply voltage Vcc = 1.4V. The CXA3117AN operates with a single power supply. 2) The CXA3117AN uses a 21.245kHz crystal. Input the RF signal from the RF pin and use the CXA3117AN in the condition where IF = 455kHz. 3) Set the mode switches. * Mode switch setting Mode switches S1, S2, S3 and S4 are provided in four locations in the board. Each basic operation can be confirmed by switching these mode switches while referring to the board layout. See the table in 15) Control Pins for the mode switching. * Device specifications See these Specifications for the IC specifications. The ICs for this evaluation board are ES specification. * Circuit diagram The circuit diagram is the same as the Application Circuit diagram in these Specifications.
- 21 -
CXA3117AN
19)-1. Standard Board Layout
VCC GND
S4
PNP
RF
24 XTAL
13 DISC
3117 EVALUATION BOARD
CERAFIL
1
12
19)-2. Mode Switch Description
Low
Slow charge
L
Sleep
S1
S3
S2
L
Slow charge operation
S3
High
Quick charge
S4
H
IC operation
H
Slow charge off
CHARGE
B. S.
CHG-OFF
L
fc: High
S1
H
fc: Low
FIL SW
- 22 -
S2
CXA3117AN
19)-3. List of Standard Board Parts VALUE PART# REMARKS (MANUFACTURE) NOTE
Resistor 220 8.7k 100k R4 R7 R5 R6 R8 (RIVER) E12 series 1/8W
Capacitor 10 to 120p 15p 22p 100p 1000p 1200p C1 C5 C4 C14 C3 C11 C12 C13 C8 C9 C10 C6 C7 25V 1 (SHIN-EI TUSHIN KOGYO CO., LTD.) 25V 10 (SHIN-EI TUSHIN KOGYO CO., LTD.) ELECTROLYTIC CAPACITOR E6 series DD100 series temperature characteristics type B (MURATA PRODUCTS) CERAMIC CAPACITOR E12 series (high dielectric constant type) TZ03P450FR169 (MURATA PRODUCTS) TRIMMER CAPACITOR
0.01 1 10
Inductor 1.8H L1 EL0405 (TDK Products) E12 series 2.5mm pitch (Lead Pitch)
Active Component PNP 2SA1015 (TOSHIBA CORPORATION)
Crystal 21.245MHz XTAL KSS 2B (KINSEKI, LTD.)
- 23 -
CXA3117AN
Ceramic Filter CERAFIL CFWS455D (MURATA PRODUCTS) 455kHz 1.5k
Ceramic Discriminator DISC CDBM455C50 (MURATA PRODUCTS) 455kHz
Switch S1, S2, S3, S4 ATE1D-2M3-10 (FUJISOKU CORPORATION) ON - ON (1 poles)
Connector RF HRM300-25 (HIROSE ELECTRIC CO., LTD.) SMA CONNECTOR
Pin x2 x6 Mac 8 test pin ST-1-3 (Mac eight) Mac 8 test pin LC-2-G (Mac eight) L = 10mm 0.8
- 24 -
CXA3117AN
Example of Representative Characteristics
Mixer input audio response and RSSI characteristics
0 S+N+D 1000
RSSI -10 RF 21.7MHz LOCAL 21.245MHz -6dBm Audio 1.6kHz CW Dev. 4.8kHz 0dB = 63.1mVrms VCC = 1.4V T = 25C 800
Audio response [dB]
-20
600
-30
400
-40
200
-50 S/N -60 -120 -110 -100 -90 -80 -70 -60 Mixer input level [dBm] -50 -40 -30
0
-20
Current consumption characteristics
1.4
Mixer I/O characteristics and 3rd intercept point
Current consumption [mA]
-20 1.3 -30
Output level [dBm]
1.2 1.1 1.0 0.9
fO -40 -50 -60 -70 f1 + f2 fO = 21.7MHz fLO = 21.245MHz -6dBm f1 = 21.725MHz f2 = 21.750MHz The I/O level is for the values read at I/O pin with the spectrum analyzer 0
1.0
2.0 3.0 Supply voltage [V]
4.0
-80 -60 -50
-40 -30 -20 -10 Mixer input level [dBm]
- 25 -
RSSI [mV]
CXA3117AN
Local input level vs. Mixer gain characteristics
10
Mixer gain [dB]
5
0
fRF 21.7MHz -60dBm fLO 21.245MHz 0.01 1
-5
50
-20
-15
-10 -5 Local input level [dBm]
0
5
Variable cut-off characteristics of audio filter
0 -10 -20 -30 Pin 12 voltage L H
Response [dB]
-40 -50 -60 100 200 500 1k 2k 5k Input frequency [Hz] 10k
Level comparator characteristics
2.0 1.8
Comparator output voltage [mV]
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 150 200 250 Comparator input voltage [mV] 300
- 26 -
CXA3117AN
Level comparator threshold value control characteristics (Output low high switching level)
Representative example using typical sample
Level comparator threshold value [mV]
300
250
210 200
150 Typical value when Pin 6 is shorted to Vcc 100 0 0.5 1.0 1.5 2.0 Pin 6 current [A] 2.5 3.0
NRZ comparator characteristics
1.6
Comparator output voltage [V]
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 160 180 200 220 240 Comparator input voltage [mV] 260
LVA characteristics
1.2
LVA comparator output voltage [V]
1.0 0.8 0.6 0.4 0.2 0 1.05 1.10 1.15 Supply voltage [V] 1.20
- 27 -
CXA3117AN
Quick charge circuit output current characteristics
0.5 Pin 7 215mV fixed 0.3
Fast mode
50
Slow mode on
30
slow current [A]
0 Slow mode off
0
-0.3
-30
-0.5
-50
80
120
160 200 240 280 Pin 11 input Pin 16 voltage [mV]
320
360
RSSI output voltage temperature characteristics
800
RSSI output voltage characteristics [mV]
700
600
500
400
300 : -20C : 0C : 25C : 50C : 75C -110 -100 -90 -80 -70 -60 RF input level [dBm] -50 -40 -30 -20
200
100 -120
- 28 -
fast current [A]
CXA3117AN
Detector output level and level comparator threshold value vs. Temperature characteristics
100 4.8kHz Dev. detector output level
Detector output level and level comparator threshold value [mV]
Level comparator threshold value for positive side 50 1.6kHz Dev. detector output level
0
Level comparator threshold value for negative side
-50
:H :L -100 -20 0 25 50 75
L H
Temperature [C]
- 29 -
CXA3117AN
Package Outline
Unit: mm
24PIN SSOP(PLASTIC)
+ 0.2 1.25 - 0.1 7.8 0.1 0.1 13
24
A
1 b
12
0.13 M B 0.65
5.6 0.1
+ 0.05 0.15 - 0.02
0.5 0.2
DETAIL B : SOLDER 0 to 10
(0.15)
0.1 0.1
(0.22)
b=0.22 0.03
DETAIL B : PALLADIUM
NOTE: Dimension "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.1g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
SONY CODE EIAJ CODE JEDEC CODE
SSOP-24P-L01 SSOP024-P-0056
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
- 30 -
+ 0.03 0.15 - 0.01
+ 0.1 b=0.22 - 0.05
7.6 0.2

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